1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and particularly to a semiconductor integrated circuit having a bonding option pin (or pad) differing in pad potential according to the sealed package type or available operation mode. More particularly, the present invention relates to the structure of an input circuit provided corresponding to the bonding option pin in such a semiconductor integrated circuit.
2. Description of the Background Art
In accordance with increase in integration density and function of a semiconductor integrated circuit, the number of input/output signals becomes greater to require more pin terminals to input/output the signals. A FP (Flat Package) having pin terminals arranged entirely around the package is employed to increase the number of pins. FIGS. 11A, 11B and 11C are a top view, front view, and a right side view, respectively, of a QFP (Quad Flat Package).
As shown in FIG. 11A, a QFP package has a rectangular feature, with pin terminals P arranged at the four sides thereof. The QFP package has a length of 20±0.1 mm, for example, in the direction of the longer side, and a length of 14±0.1 mm, for example, in the direction of the shorter side. An external pin terminal P has a length of approximately 2.0 mm. In FIG. 11A, a plurality of pin terminals P are arranged along all the longer and shorter sides. In the direction of the longer side, pin terminals with the pin numbers of #1–#30 and #51–#80 are arranged opposite to each other. In the shorter sides, pin terminals of pin numbers #31–#50 and #81–#100 are arranged opposite to each other.
As shown in FIGS. 11B and 11C, pin terminals P each have a gull wing shape (L shape). A pin terminal P is led out from the center area at the side surface of the package. The flat portion of the end of the L shape is substantially in flush with the bottom of the QFP package.
FIG. 11D shows an enlargement of a portion 30B of FIG. 1B. In FIG. 11D, pin terminal P is led out from the side surface of a package PK formed of sealing resin with its shape formed into a gull wing. The bottom portion (flat portion) of this pin terminal P is set to have an extremely small difference in height with the bottom of package PK. Therefore, the height of this QFP is as low as approximately 1.6 mm. Pin terminal P has the flat portion soldered to a wiring of a printed circuit board. The QFP is widely used as a surface-mount type package.
The pin terminal pitch of the QFP is, for example, 0.65 mm. The pin terminal pitch (the interval between pin terminals) becomes smaller as the number of pin terminals becomes greater. The pin terminal (lead terminal) is thin and easily deformed. In mounting the package on the printed circuit board, there is a possibility that the pin terminal is deformed to disable proper soldering to the printed circuit board (the pin terminal may be offset in position or short-circuited or damaged). A ball grid array type (BGA) package (solder ball array arrangement type package) having many terminals arranged without degrading the terminal pitch are beginning to be used for accommodating increase in the number of pin terminals.
FIGS. 12A, 12B, and 12C are the front view, right side view, and back surface view, respectively, of a ball grid array type package.
As shown in FIG. 12A, the ball grid array type package has a mold resin MR formed on a substrate BAS at the top surface thereof. A semiconductor integrated circuit is sealed by this mold resin MR. As shown in FIG. 12B, solder balls SB are arranged in alignment at the back surface of substrate BAS.
Solder balls SB are arranged in a matrix of rows and columns at the back surface of substrate BAS as shown in FIG. 12C. FIG. 12C shows an example of solder balls SB arranged in a matrix of columns 1–9 and rows A–U.
In the BGA (Ball Grid Array type) package, a solder ball SB has a diameter of approximately 0.76 mm. The pitch of the solder balls SB is approximately 1.27 mm. Solder ball SB has a height of approximately 0.60 mm. The package has a height of approximately 2.06 mm with solder ball SB included. The mold resin has a length of approximately 19.50 mm in the direction of the longer side and approximately 12.00 mm in the direction of the shorter side.
In a BGA package, solder ball SB formed at the back surface of substrate BAS is electrically connected to a solder pad formed on the printed circuit board.
In a BGA package, solder ball SB corresponds to a pin terminal in the QFP package. Therefore, the terminal pitch in a BGA package can be made larger than that of a QFP package. This means that more pin terminals can be arranged in a limited area, so that the package area can be reduced. Since solder ball SB is a hard ball, the possibility of deformation caused by contact is smaller in on-board-mounting. Since solder ball SB is electrically connected (reflow soldering) to the solder pad formed at the printed circuit board, the inductance of the lead terminal (pin terminal) is small.
However, there is a possibility that moisture adsorbed will be expanded by the reflow heat during reflow-soldering to cause detachment between the board or mold resin and the semiconductor integrated circuit chip, or to cause the generation of a crack in the mold resin and/or board. When the terminal pitch is excessively made small in a BGA package, the total number of wirings on the printed circuit board will increase to cause higher cost for the mounting board. Also due to the usage of a double-side printed circuit board for the BGA package the warp of the board induces variation in the height of the terminal in the package caused, to result in difference in contact degree of the solder balls.
Thus, the package for a semiconductor integrated circuit device is selected according to its usage, taking into account respective features of the QFP and BGA packages.
Consider a synchronous burst SRAM (Static Random Access Memory) as an example of a semiconductor integrated circuit. This synchronous burst SRAM allows continuous writing/reading of data of a predetermined burst length according to an externally applied clock signal.
FIG. 13 schematically shows an entire structure of a conventional synchronous burst SRAM. Referring to FIG. 13, synchronous burst SRAM 100 includes a memory array 102 with a plurality of static type memory cells arranged in rows and columns, an address register 104 taking in an address signal AD in synchronization with an externally applied clock signal CLK, a burst counter 106 taking in the least significant two bits of the address signal from address register 104 to sequentially change the input two bits at a predetermined sequence for output, and an address control circuit 108 taking in an address advance /ADV, an address status processor /ADSP, and an address status controller /ADSC in synchronization with clock signal CLK, to control the operation of address register 104 and burst counter 106 according to the status of these signals.
Address control circuit 108 causes burst counter 106 to carry out a count operation when address advance /ADV is at an L level at the rising edge of clock signal CLK. Address control circuit 108 causes address register 104 to input an externally applied address signal AD and burst counter 106 to stop its burst operation for taking in the least significant 2 bits of the address signal from address register 104.
The sequence of altering the input address signal bits in burst counter 106 is determined by a burst mode control MODE. By this burst mode control MODE, burst counter 106 carries out a linear burst operation of sequentially incrementing the input address by 1, or an interleaved burst operation of sequentially changing the more significant bit and less significant bit. In the synchronous burst SRAM, burst counter 106 carries out a count operation to change the address signal when address advance /ADV is at an L level at the rising edge of clock signal CLK. Therefore, an address signal is generated internally without applying an external address signal AD at each clock cycle to address a memory cell in memory array 102.
Synchronous burst SRAM 100 further includes a write control circuit 110 taking in a write enable control /WE and a chip select control /CS in synchronization with clock signal CLK, to perform control required for a write operation in synchronization with clock signal CLK, an input register 112 for taking in an externally applied data D (DQ) in synchronization with clock signal CLK under control of write control circuit 110, and a write circuit 114 for writing the data applied from input register 112 to an addressed memory cell in memory array 102 under control of write control circuit 110. Write control circuit 110 stops the write operation by an output enable /OE.
Write enable control /WE includes a master byte write /MBW to permit data writing in units of bytes, a global write /GW for writing simultaneously into the memory cells of all the bits (for example 32 bits), and byte write /BW1, /BW2, /BW3 and /BW4 to control data writing on a byte-by-byte basis. In a data writing operation, data writing can be controlled (masked) on a byte-by-byte basis. Therefore, input register 112 transfers internal write data on a byte-by-byte basis under control of write control circuit 110.
Synchronous burst SRAM 100 further includes an output control circuit 118 for generating an output control signal according to output enable /OE and the output signal of write control circuit 110, an output register 116 for reading out and latching the data of a selected memory cell in memory array 106, and an output buffer 120 for sequentially outputting the latched data of output register 116 under control of output control circuit 118.
Write control circuit 110 stops the write control operation at a next cycle to enable output control circuit 118 when output enable /OE attains an active state of an L level. Output control circuit 118 drives output buffer 120 from an output high impedance state to an output low impedance state according to output enable /OE under the enabled state to sequentially output the data read out from output register 116. Output register 116 responds to flow through /FT to transfer the read out data to output buffer 120 in a pipeline manner according to clock signal CLK, or to transfer the data read out from memory array 102 directly to output buffer 120 in a non-pipeline manner ignoring clock signal CLK. Snooze mode control ZZ is applied to each circuit to suppress the operation of each circuit when activated to reduce current consumption.
Synchronous burst SRAM 100 receives power supply voltage VDD and VSS as operating power supply voltages for the internal circuitry, and voltage VDDQ and VSSQ as the operating power supply voltages for the input/output buffer circuit. By providing power supply voltages VDDQ and VSSQ for use by the input/output buffer circuit separately from power supply voltages VDD and VSS for use by the internal circuit operation, variation in power supply voltages VDDQ and VSSQ, if occurring, in the input/output buffer operation, can be prevented from adversely affecting the internal circuit operation. Also, the input/output circuitry can be operated stably. Voltage VDDQ is approximately 1.8 V and voltage VDD is approximately 3.3 V. A signal can be transmitted speedily over the board.
To meet the requirement of the user developing a system or an electronic device using this synchronous burst SRAM, the synchronous burst SRAM may be sealed in a QFP package representative of a flat package or in a solder ball array arrangement type package having solder balls attached to the back surface of the package in an array, represented of a BGA package. A pin arrangements coping with both the packages of QFP and BGA are proposed by JEDEC (Joint Electron Device Engineering Council) so that both QFP and BGA packages can be used.
FIG. 14 shows the allocation of a signal with respect to each pin terminal in a QFP package. In FIG. 14, the pin arrangement of a 32K 36-bit synchronous burst SRAM is illustrated. In the region where pin terminals are arranged from pin number 1 to 30 in FIG. 14, data input/output bit DQ, flow through control FT# (/FT), and power supply voltages Vddq, Vssq, Vdd, Vss are allocated. The reason why the pin terminal receiving the power supply voltage is arranged between the pin terminals receiving the data bits is to supply a power supply voltage to the data input/output buffer circuitry stably. Flow through control FT# (/FT) is applied to the pin terminal of number 14.
Burst mode control LBO# (MODE) specifying the count sequence of the burst counter and an address signal AD (SA, SA1, SA0) are allocated to the pin terminals of numbers 31–50.
Data DQ and power supply voltages Vddq, Vssq, Vdd and Vss are allocated to the pin terminals of numbers 51–80. The allocation of the signals allocated to the pin terminals of numbers 51–80 is identical to that of the signals allocated to the opposite pin terminals of numbers 1–30. Snooze mode control ZZ is applied to the pin terminal of number 64. Snooze mode control ZZ functions to reduce the current consumption significantly by suppressing all the internal circuitry operation. According to the structure of the burst SRAM of FIG. 13, snooze mode control ZZ is applied to each circuit to fix the output signal level thereof.
Address signal AD and respective control signals are allocated to the pin terminals of numbers 81–100. Signals SE1#, SE2# and SE3# correspond to chip select /CS. Signals SBWd#, SBWc#, SBWb#, SBWa#, SGW# and SBWE# correspond to write enable control /WE. Signal G# corresponds to output enable /OE. Signal CK corresponds to clock signal CLK.
Signal SAC# corresponds to address status control /ADSC. Signal SAP# corresponds to address status processor /ADSP. Signal SADV# corresponds to address advance control #ADV.
By arranging data input/output pins at both sides of the package while arranging address signal AD and control signals at opposite sides, the memory array structure is made symmetrical to allow simplification of the internal layout.
FIG. 15 shows the signal allocation with respect to a solder ball (bump) in a BGA package. In the BGA package corresponding to FIG. 15, solder balls (bump) are arranged in 17 rows (rows A–U)×7 columns with signals allotted respectively. A the first column, data and power supply voltages are allocated. At the second column, addresses and data are allocated. At the third column, control signals, power supply voltages, and address signal bits are allocated. At the fourth column, control signals and power supply voltages are allocated. At the fifth column, control signals and address signal bits are allocated. At the sixth column, data and address signals are allocated. At the seventh column, data bits and power supply voltages are allocated. The label (reference character) of each signal is the same as shown in FIG. 14.
In FIGS. 14 and 15, reference character NC indicates “no connection”. The corresponding pin terminal is not connected to a wire when mounted on a board.
In the allocation shown in FIG. 15, signals TMS, TDI, TCK, TDO and TRST are allocated at row U, which are the control signal, test clock signal, and test data signal used in a boundary scan test circuit. The reason why this boundary scan test and these signals data are allocated in a BGA package will be explained now.
FIG. 16 schematically shows a structure of a board formed by a test-designed chip according to the boundary scan design. Referring to FIG. 16, a plurality (in this case, 4) of semiconductor chips 152a, 152b, 152c and 152d are arranged on a board (printed circuit board) 150. Each of chips 152a–152d may be a semiconductor integrated circuit device that realizes the same logical function, or a semiconductor integrated circuit that realizes a function of a semiconductor memory device. Chip 152 (generically representative of chips 152a–152d) includes an input/output terminal 154 (generically representative of terminals 154a–154d) to input/output data that is to be processed or that is processed in a normal operation, a boundary scan register (BSR) 155 (generically representative of boundary scan registers 155a–155d) including at least the function to transmit test data, and an internal logic 153 (generically representative of internal logics 153a–153d; synchronous burst SRAM of FIG. 13, for example, corresponds to the same) for executing a desired logical operation.
Boundary scan register 155 is provided corresponding to each data input/output terminal (pad) 155. More specifically, boundary scan register 155 is provided corresponding to each input/output buffer. Also, boundary scan register 155 is connected in series to form a serial data shift path in one chip. The boundary scan register of each chip is connected in series via shift path 156. Accordingly, boundary scan registers 155 of chips 152a–152d forms one serial test data transfer path on board 150.
Input/output terminals 154a, 154b, 154c and 154d of chips 152a–152d, respectively, are connected to each other via system signal lines 157. A data signal that is to be processed or that is processed is delivered on system signal line 157 in a normal operation.
A board input/output terminal region (edge connector) 158 is provided on board 150 to transfer data between chip 152 on board 150 and another device external to board 150 (a chip on another board or test apparatus). Edge connector 158 includes input/output terminals 158a, 158b, and 158c for the input/output of process data SD in a normal operation at the board level, a scan-in terminal 159 receiving test data TDI, and a scan-out terminal 160 for providing test data TDO. Test data TDI applied to scan-in terminal 159 is transferred in series via the scan path formed of boundary scan registers 155 provided in each of chips 152a–152d. The scan-in test data TDI is set at a desired boundary scan register 155 by being sequentially transported via the boundary scan path.
Scan-out terminal 160 receives in series test data TDO transmitted via the scan path formed of boundary scan registers 155 provided in chips 152a–152d on board 150. Test data TDO can be read out from an arbitrary boundary scan register 155.
Boundary scan register 155 is provided corresponding to each input/output terminal 154 to shift applied test data, and to latch data from internal logic 153 or the data applied to input/output terminal 154.
The clock signal to control the shift operation of boundary scan register 155 is applied by a test clock signal TCK different from the system clock by which chips 152a–152d on board 150 operate. Since the test data transportation path is separated from the transportation path of system data (write/read data of memory, control signal, address signal), boundary scan register 155 can receive processed data of internal logic 153 without adversely affecting the operation of internal logic 153.
As shown in FIG. 16, by providing boundary scan registers in respective chips and connecting these registers to form a data transfer path, a particular chip 152 on board 150 can be directly accessed from edge connector 158 of board 150. Thus, a desired chip 152 on board 150 can be tested without using an expensive in-circuit tester. Furthermore, testing can be performed easily even in the case of a chip that is difficult to form contact between a test probe and a chip terminal such as in the case of a surface-mounted component.
Such a boundary scan test scheme using a boundary scan register includes an internal test, an external test, and a sample mode. In an internal test, desired data is set at a boundary scan register via the scan path to operate the internal logic. Determination is made on whether this internal logic operates properly or not. In an external test, a wiring between chips (line on board 150; system signal line 157) is tested. In external testing, the test data for confirming the connection is transmitted via shift path 156 to be retained in boundary scan register 155 connected to the output terminal of chip 152. This connection-confirmation test data is then applied to a corresponding output terminal. The test data applied to the output terminal is input to a boundary scan register connected to the input terminal of another chip. The data received by the boundary scan register is propagated on shift path 156 to be output from scan-out terminal 160. By observing this output data TDO, confirmation can be made on whether the interconnection of system signal line 157 between the chips is proper or not. By this external test, the open-and short-circuited states of lines between chips caused by chip line disconnection and defective soldering between a chip and a board can be tested.
For example, in chips 152a, 152b, 152c and 152d in FIG. 16, boundary scan register 155c of chip 152 is the boundary scan register connected to the output terminal. Boundary scan register 155a of chip 152a and boundary scan register 155d of chip 152d are boundary scan registers connected to the input terminal. In this case, the signal from the output terminal corresponding to boundary scan register 155 is applied to the input terminal corresponding to boundary scan registers 155a and 155d via system signal line 157.
The operation of testing the connection between boundary scan register 155c and boundary scan registers 155a and 155d will be described briefly now. First, connection-confirmation test data is sent to boundary scan register 155c via shift path 156 to be retained therein. The connection-confirmation test data retained in boundary scan register 155c is sent to boundary scan registers 155a and 155d of chips 152a and 152d, respectively, via a corresponding output terminal of chip 152c to be retained.
The connection-confirmation test data input to boundary scan registers 155a and 155d is output from scan-out terminal 160 via shift path 156. By observing data TDO output from scan-out terminal 160, the connection of signal line 157 between chips 152a and 152d and chip 152c is confirmed. This operation is performed on the input/output terminals between chips that are interfaced. By this test, interconnection failure between chips, i.e. the open-and short-circuited states caused by chip line disconnection and soldering defect between the chip and board, can be tested.
As to the above-described boundary scan test, a standard is proposed by the JTAG (Joint Test Action Group).
As shown in FIG. 12, BGA package has the solder balls arranged at the bottom of the package, so that the connection between the solder and the wire of the printed circuit board cannot be viewed. Also, the BGA package is a surface-mount type package, so that the pin (probe) of an in-circuit tester cannot attach the package pin. In a QFP package, the pin terminals are arranged at the surface of the printed circuit board as shown in FIG. 11A even though it is a surface mount type package. Therefore, the solder junction portion can be viewed. When a package passes an electrical characteristic test with a lead terminal merely placed on the solder and the junction not formed, such a defective junction can be found out by a visual inspection of the solder junction. In the case of a BGA package, visual inspection of the junction portion cannot be carried out since the terminal is located at the bottom of the package. Therefore, a boundary scan test circuit according to the above-described scan design method is provided in the semiconductor integrated circuit. By carrying out this boundary scan test after the BGA package is mounted on the printed circuit board, the short-circuited/open state of each line can be examined to assure reliability of the memory system after mounting.
Synchronous burst SRAM has to have the boundary scan test set to an executable state when sealed in a BGA package. When it is sealed in a QFP package, the boundary scan test is not required. Modification of the internal structure of a synchronous burst SRAM having a common function according to the type of the sealing package will degrade the design efficiency and fabrication efficiency. Therefore, a boundary scan test circuit is formed regardless of the type of the package to selectively connect a pad for the test circuit and a corresponding pin terminal depending upon the package type at the bonding step. Thus, a synchronous burst SRAM of the same function can be formed into a product through the same processings step by only modifying the bondings in the bonding step. As a result, the production efficiency and the design efficiency can be improved.
FIG. 17 schematically shows an entire structure of a conventional synchronous burst SRAM having a built-in test circuit. Referring to FIG. 17, the synchronous burst SRAM includes an input/output buffer group 160 arranged at the periphery, a boundary scan register group 165 with boundary scan registers provided corresponding to respective input and output buffers in input/output buffer group 160 to form a serial transfer path, a test control circuit 167 for effecting control of the boundary scan test, and an internal circuit 169 carrying out a predetermined function.
Test control circuit 167 sequentially transfers test input data TDI to boundary scan register group 165 according to externally applied test mode select signal TMS, test mode reset signal TRST, and test clock signal TCK through input/output buffer group 160 to carry out the test specified by test mode select signal TMS. Test result data TDO retained in the registers in boundary scan register group 165 are output sequentially by the shift operation of boundary scan register group 165 under control of test control circuit 167. Internal circuit 169 includes the circuit structure shown in FIG. 13.
The boundary scan test circuit formed of boundary scan register group 165 and test control circuit 167 is not coupled to an external terminal since a pin terminal is not allocated thereto when sealed in the QFP package. More specifically, the pads provided corresponding to signals TMS, TRST, TCK and data TDI and TDO are not connected to the external pin terminals. Therefore, it is necessary to prevent an unused boundary scan test circuit from operating erroneously and to prevent extra current from being consumed when sealed in the QFP package.
There is a signal having a pin terminal allocated independent of the package type, but has the connection between the pin terminal and a corresponding internal pad selectively established through a bonding wire or has the pin terminal fixed to a different potential, depending on the sealing package type. The operation mode to be carried out internally is determined by selective connection or selective setting of the pad potential in the step of making a bonding between a pin terminal and a corresponding pad. Such a pad is referred to as a “bonding option pad” hereinafter.
FIG. 18 shows an example of a signal related to a bonding option pad. In FIG. 18, three control signals are shown, i.e., a flow through signal /FT (FT#), a burst mode signal MODE (LBO#), and a snooze mode signal ZZ. When the pad corresponding to flow through signal /FT (FT#) is set at an H level or at an NC state, a normal mode (pipeline operation mode) is set in which data is output in synchronization with clock signal CLK. When flow through signal /FT (FT#) is fixed at an L level, the flow through mode (non-pipeline) is selected. The clock synchronized operation of the output register is ceased, and data is output statically. Here, an NC state indicates a state where a pad and a corresponding pin terminal is not connected by a bonding wire, or when a pin terminal is not connected to an internal line.
Burst mode signal MODE (LBO#) specifies an interleaved burst mode when the corresponding pad is set to an H level or an NC state and specifies a linear burst mode when the corresponding pad is fixed at an L level. In an interleaved burst mode, address signal (A1, A0) changes cyclically in the order of (A1, A0)→(A1, /A0)→(/A1, A0)→(/A1, /A0) in burst counter 106 of FIG. 13. In a linear burst mode, address bits (A1, A0) change cyclically in the order of (0, 0)→(0, 1)→(1, 0)→(1, 1) according to the value of the initially input address bits. Flow through signal /FT (FT#) and burst mode signal MODE (LBO#) have their pad potentials fixed in packaging or board-mounting, so that the states thereof will not change in a normal operation.
Snooze mode signal ZZ sets a normal operation mode when the corresponding pad is at an L level or an NC state, and sets a snooze mode when the corresponding pad is at an H level. In a normal operation mode, access is effected according to external clock signal CLK. In a snooze mode, the input/output buffer does not operate, so that the state of the internal circuit will not change independent of application of external clock signal CLK. Since the internal circuit does not operate and the potential level of the internal signal does not change when the snooze mode is set, a state where the power supply current is extremely low is set. In the case of snooze mode signal ZZ, a synchronous burst SRAM operable in a snooze mode and a synchronous burst SRAM disabled of the snooze mode operation are set by the absence/presence of bonding with respect to this pad.
In a semiconductor integrated circuit that includes only a required function among a plurality of functions, all the plurality of functions are implemented in the integrated circuit, and only the required function is set by the absence/presence of bonding/wiring to simplify the fabrication step, to shorten the turn around time, and to improve the design efficiency. The bonding option pad is set to a floating state, or bonded to the power supply line/ground line. In this case, the internal signal state must be set to a predetermined voltage level even in a floating state (NC state).
FIG. 19 shows an example of a structure of the input portion of the bonding option pad. Referring to FIG. 19, an input protection circuit formed of diodes D1 and D2, and a buffer circuit Bufa for buffering the potential of the signal on a pad PDa are provided with respect to pad PDa. Diode D1 has its anode connected to pad PDa and its cathode connected to a power supply node receiving power supply voltage VDD. Diode D2 has its cathode connected to pad PDa and its anode connected to ground node. A pull up resistor R1 is also provided with respect to pad PDa. Pull up resistor R1 pulls up the potential at the input portion of buffer Bufa to the level of power supply voltage VDD.
Pad PDa is selectively connected to a corresponding pin terminal PTa by a bonding wire BWa. A signal φph applied to pin terminal PTa is a burst mode signal LBO# (MODE) or flow through signal FT# (/FT) in the example of FIG. 18. When bonding wire BWa is not provided or when the pin terminal is at an NC state, the potential at the input of buffer Bufa is set to the level of power supply voltage VDD by pull up resistor R1. When pad PDa is connected to pin terminal PTa by bonding wire BWa, no current flows through pad PDa if signal φph is at an H level.
However, when signal φph is set at an L level, current i flows from pull up resistor R1 to the ground of pin terminal PTa through pad PDa and bonding wire BWa. Signal φph is either burst mode signal LBO# or flow through signal FT# and set to either an H or L level. Therefore, when pin terminal PTa is set to a logic level opposite to that set by pull up resistor R1, there is a problem that current flows from pull up resistor R1 to increase power consumption. Particularly in a standby state, this current attains a level that cannot be negligible even when the resistance value of pull up resistor R1 is large enough.
FIG. 20 shows another structure of the input portion with respect to a bonding option pad. Referring to FIG. 20, an input protection circuit formed of diodes D3 and D4, and a buffer Bufb are provided with respect to pad PDb. Diode D3 is connected in a forward direction from pad PDb to the power supply node. Diode D4 is connected in a reverse direction from pad PDb to the ground node. A pull down resistor R2 having a relatively large resistance is provided at the input of buffer Bufb.
Pad PDb is selectively connected to a corresponding pin terminal PTb via bonding wire BWb. A signal φpl applied to pin terminal PTb is, for example, a snooze mode signal ZZ. When bonding wire BWb is not provided and pin terminal PTb is disconnected from pad PDb or when pin terminal is at an NC state, the potential of pad PDb is maintained at the level of the ground voltage by pull down resistor R2. When pin terminal PTb and pad PDb are connected to each other by bonding wire BWb, current does not flow through pad PDb, bonding wire BWb and pin terminal PTb when signal φpl is at an L level. When signal φpl is at an H level, current flows from pin terminal PTb via bonding wire BWb, pad PDb and pull down resistor R2. In the case where signal φpl is a snooze mode signal ZZ, the device is operable in the snooze mode when pad PDb is connected to pin terminal PTb by bonding wire BWb. When the snooze mode is set, snooze mode signal ZZ is at an H level. Therefore, current flows from pin terminal PTb via pad PDb and resistor R2. Current will be consumed unnecessarily in a snooze mode implemented for reducing power consumption.
The above problem arises in the case where the function of the internal circuitry is set depending upon the presence/absence of pad bonding.